Panasonic MN103001G/F01K Manuale Utente

MICROCOMPUTER MN1030MN103001G/F01KLSI User’s ManualPub.No.23101-050E

iiTable of Contents1. General Specifications1.1 Overview ...

Memory Modes4-44.3 Description of Memory Mode4.3.1 Memory Extension ModeThe memory mode which comprises a system from both internal and external memor

Memory Modes4-54.3.2 Processor ModeThe memory mode which executes externally located instructions while using the internal data RAM and I/O p

Memory Modes4-6

5. Operating Mode5

Operating Mode5-25.1 OverviewThe 32-bit microcontroller has the following three operating modes. Oscillator start/stop and CPU and peripheralcircuit s

Operating Mode5-35.2 Reset Mode• The mode in which the reset (RST) pin is active (“L” level) is called “Reset Mode”.• When the reset pin is low, the c

Operating Mode5-45.3 Low Power ModeLow power consumption is achieved by stopping the oscillation of the oscillators and the clock generator (CG) andst

6. Clock Generator613

Clock Generator6-26.1 OverviewThe CG has an internal PLL circuit; in addition to supplying clock pulses to this microcontroller at a frequency thatis

Clock Generator6-36.4 Description of Operation6.4.1 Input Frequency SettingThe CG input frequency range is set by the external input pin CKSEL. When

iii5. Operating Mode5.1 Overview ...

Clock Generator6-4The relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequenciesis shown in Table 6-4-

7. Internal Memory7

Internal Memory7-27.1 OverviewThe MN103001G has 128 Kbytes of instruction ROM and 8 Kbytes of internal data RAM. The MN1030F01K has256 Kbytes of flas

Internal Memory7-37.3 Internal Memory ConfigurationThe internal instruction ROM is located in the internal memory space at address x'40000000 to

Internal Memory7-4

8. Bus Controller (BC)8

Bus Controller (BC)8-28.1 OverviewThe bus controller (BC) controls interfacing between the CPU core, internal I/O (peripherals), and devices externalt

Bus Controller (BC)8-38.3 Bus ConfigurationFig. 8-3-1 shows the bus configuration. The chip’s internal buses are the ROM bus between the CPU core and

Bus Controller (BC)8-4Fig. 8-4-1 Block Diagram for the Bus ControllerBC address busBC data busI/O address busI/O data busBC internal data busBC bus

Bus Controller (BC)8-58.5 Pin FunctionsThe external pin functions relating to the bus controller are shown in Table 8-5-1.Table 8-5-1 External Pin F

iv8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and inAddress/Data Separate Mode...

Bus Controller (BC)8-6Table 8-5-2 shows the operating status of the external pins concerning BC.Table 8-5-2 Operating Status of Pins Concerning BCOp

Bus Controller (BC)8-78.6 Description of RegistersTable 8-6-1 lists the bus controller registers. The settings of these registers are used in timing

Bus Controller (BC)8-8~~~~~~~~8.6.1 Memory Block 0 Control RegisterMemory control register 0A/B is used to set the memory block 0 read/write timing an

Bus Controller (BC)8-9~~~~~~Memory control register 0BRegister symbol: MEMCTR0BAddress: x’32000020Purpose: Sets the bus mode, access timing, etc., for

Bus Controller (BC)8-108.6.2 Memory Block 1 Control RegisterMemory control register 1A/B is used to set the memory block 1 read/write timing, synchron

Bus Controller (BC)8-11~~~~~~~~~~When using DRAM (Memory control register 1B B1DRAM = 1)Bit No. Bit name Description Setting conditions1 to 0 BCS1 to

Bus Controller (BC)8-12~~~~~~Memory control register 1BRegister symbol: MEMCTR1BAddress: x’32000022Purpose: Sets the bus mode, access timing, etc., fo

Bus Controller (BC)8-13When using DRAM (Memory control register 1B B1DRAM = 1)Bit No. Bit name Description Setting conditions0 DRAM Block 1 DRAM 1: U

Bus Controller (BC)8-148.6.3 Memory Block 2 Control RegisterMemory control register 2A/B is used to set the memory block 2 read/write timing, synchron

Bus Controller (BC)8-15When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1)Bit No. Bit name Description Setting conditions1

v10.6 Description of Operation... 10-2010.6.1 Interval Timers

Bus Controller (BC)8-16When using fixed wait mode and not using DRAM (Memory control register 2B B2DRAM = 0, B2WM = 0)Bit No. Bit name Description S

Bus Controller (BC)8-17~~~~~~~~When using DRAM (Memory control register 2B B2DRAM = 1 B2WM = 0)Bit No. Bit name Description Setting conditions0 DRAM B

Bus Controller (BC)8-18After the reset is released, block 2 is set as follows:Address output end timing 3MCLKRE negate timing 29MCLKWE negate timing 2

Bus Controller (BC)8-198.6.4 Memory Block 3 Control RegisterMemory control register 3A/B is used to set the memory block 3 read/write timing, synchron

Bus Controller (BC)8-20When using handshaking mode (Memory control register 3B B3WM = 1)Bit No. Bit name Description Setting conditions1 to 0 BCS1 to

Bus Controller (BC)8-21When using handshaking mode (Memory control register 3B B3WM = 1)Bit No. Bit name Description Setting conditions1 WM Block 3 wa

Bus Controller (BC)8-228.6.5 DRAM control registerDRAM control registerRegister symbol: DRAMCTRAddress: x'32000040Purpose: Stores various DRAM mo

Bus Controller (BC)8-23~~8.6.6 Refresh count registerRegister symbol: REFCNTAddress: x'32000042Purpose: Sets the DRAM refresh interval when DRAM

Bus Controller (BC)8-248.6.7 Page Row Address RegisterPage Row Address RegisterRegister symbol: PRARAddress: x'32000044Purpose: Sets the row addr

Bus Controller (BC)8-25Notes when switching the internal clock multiplierBe aware of the following points when setting the clock control register CKCT

vi13.4.2 Block Diagram of UART Serial Interface ... 13-3713.4.3 Description of Registers for the UART Ser

Bus Controller (BC)8-268.7 Space PartitioningIn extension memory mode (MMOD 1 to 0 = "LH"), the 1 GB memory space from x'80000000 to x&

Bus Controller (BC)8-27Fig. 8-7-2 Space Partitioning1 GBProcessor modeSystemreserved2 GB1 GBInternal memory spaceExternal memory spaceExternal memor

Bus Controller (BC)8-288.8 Operation ClocksMCLK, IOCLK, and SYSCLK are used as BC operation clocks. Table 8-8-1 shows the ratio of each clock versust

Bus Controller (BC)8-298.10 Bus CycleDepending on the value of the external input pin CKSEL and the internal registers, the MCLK frequency can beeithe

Bus Controller (BC)8-308.11 Store BufferThe bus controller has one store buffer (with a 32-bit data width) built in, and is used to avoid a time penal

Bus Controller (BC)8-318.12 Accessing the Internal I/O SpaceAccesses to the internal I/O space (I/O register) are performed through the I/O bus, with

Bus Controller (BC)8-328.13 External Memory Space Access (Non-DRAM Spaces)During an access to external memory, the BC controls the interface for the r

Bus Controller (BC)8-338.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate ModeSetting of the various parameter

Bus Controller (BC)8-34AnDnWEnRECSnEAMCLKSYSCLKBCSBCEBCSBCERENEAWENWriteRead:UndefinedFig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States

Bus Controller (BC)8-358.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate ModeWhen using handshaking, bus access sta

vii15.9.3 Pin Configurations ... 15-4415.10 Port 8 ...

Bus Controller (BC)8-36Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK =

Bus Controller (BC)8-37AnDnWEnRECSnEAMCLKSYSCLKEAReadWriteBCEBCERENWEN: Undefined8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate M

Bus Controller (BC)8-38AnDnWEnRECSnEAMCLKSYSCLKEA Read Write BCEBCERENWEN: UndefinedFig. 8-13-9 Access Timing on a 16-bit Bus in Asynchronous Mode an

Bus Controller (BC)8-398.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode8-bit bus mode is set for block 0

Bus Controller (BC)8-40AnD7-0WE0RECSnMCLKSYSCLKRead low-order sideRead high-order sideWrite low-order sideWrite high-order sideA[0]=0BCEBCSA[0]=1BCEBC

Bus Controller (BC)8-418.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode8-bit bus mode is set for blocks 2 and

Bus Controller (BC)8-42(a) Read Timing(b) Write TimingFig. 8-13-13 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address

Bus Controller (BC)8-43Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYS

Bus Controller (BC)8-44(a) Read Timing(b) Write TimingFig. 8-13-15 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address

Bus Controller (BC)8-458.13.6 8-bit Bus in Asynchronous Mode and in Address/Data Separate Mode8-bit bus mode is set for block 0 by setting the mode th

viiiList of Figures and TablesList of Figures1. General SpecificationsFig. 1-3-1 MN103001G Block Diagram ...

Bus Controller (BC)8-46Fig. 8-13-17 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK

Bus Controller (BC)8-47Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK

Bus Controller (BC)8-488.13.8 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex ModeBy setting the mode through the MMOD1

Bus Controller (BC)8-49Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and inAddress/Data Multiplex Mode (MCLK = SYSC

Bus Controller (BC)8-50Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and inAddress/Data Multiplex Mode (MCLK = SYSC

Bus Controller (BC)8-518.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex ModeBy setting the mode through the MMOD1 and 0 pins and t

Bus Controller (BC)8-528.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex ModeBy setting the mode through the

Bus Controller (BC)8-53(a) Read TimingFig. 8-13-24 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and inAddress/Data Multipl

Bus Controller (BC)8-54Fig. 8-13-25 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and inAddress/Data Multiplex Mode (MCLK =

Bus Controller (BC)8-55(b) Write TimingFig. 8-13-26 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and inAddress/Data Multip

ixFig. 8-7-1 Address Format When Accessing External Memory ... 8-26Fig. 8-7-2 Space Partitioning...

Bus Controller (BC)8-568.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex ModeBy setting the mode through the MMOD1

Bus Controller (BC)8-57Fig. 8-13-27 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSC

Bus Controller (BC)8-58(a) Read TimingFig. 8-13-28 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/Data Multiplex Mod

Bus Controller (BC)8-59(a) Read Timing(b) Write TimingFig. 8-13-29 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/Da

Bus Controller (BC)8-608.13.12 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex ModeBy setting the mode through the MMOD1 and 0 pins and t

Bus Controller (BC)8-61(b) Write Timing(a) Read TimingFig. 8-13-30 Access Timing on a 8-bit Bus in Asynchronous Mode and inAddress/Data Multiplex Mode

Bus Controller (BC)8-628.14 External Memory Space Access (DRAM Space)8.14.1 DRAM SpaceBlocks 1 and 2 can be used as DRAM space by setting the BnDRAM b

Bus Controller (BC)8-63 Minimum value for the RAS Precharge intervalWhen consecutive DRAM accesses are performed, the RAS precharge interval is short

Bus Controller (BC)8-64 2 WE control/2 CAS controlDRAM that permits byte/word control can be supported by selecting either one of the following two m

Bus Controller (BC)8-658.14.2 DRAM page modeIf the PAGE bit in the DRAM control register is set to “1”, page mode access is enabled, making high-speed

xFig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode andin Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ..

Bus Controller (BC)8-668.14.3 Software Page ModeSoftware page mode is a mode that forcibly initiates page mode by setting the control register.Operati

Bus Controller (BC)8-67MCLKRowCAO+1AnCASREDnASRRASnColumnCASASCColumnCASColumnCASASC ASCMCLKRowCAO+1AnCASWEnDnASRRASnColumn ColumnCASASC ASCCASASCCASC

Bus Controller (BC)8-68[Restrictions on Use](1) While software page mode is in effect, external access outside of the block in question is prohibited.

Bus Controller (BC)8-69Fig. 8-14-8 DRAM Refresh TimingFor details on the ASR and RP settings, refer to the explanations in section 8.6.2, “Memory Bloc

Bus Controller (BC)8-708.15 Bus ArbitrationIn this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and t

Bus Controller (BC)8-71Fig. 8-15-1 Bus Arbitration Timing 1(Bus Authority Release/Bus Authority Acquisition, nfr = 4)Fig. 8-15-2 Bus Arbitration Timin

Bus Controller (BC)8-72Fig. 8-15-3 Bus Arbitration Timing 3(Bus Authority Release/Bus Authority Acquisition, nfr = 1)Fig. 8-15-4 Bus Arbitration T

Bus Controller (BC)8-738.16 CautionsThese cautions concern the BC. These cautions must be heeded, since failure to do so may result in misoperation.1

Bus Controller (BC)8-742._____Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release_____pin (BG)

9. Interrupt Controller9

xi10. 8-bit TimersFig. 10-3-1 8-bit Timer Block Diagram (Timers 0 to 3) ... 10-3Fig. 10-3-2 8

Interrupt Controller9-29.1 OverviewThe interrupt controller processes non-maskable interrupts and level interrupts (internal interrupts and externalin

Interrupt Controller9-39.4 Block DiagramFig. 9-4-1 Block Diagram 1Interrupt controlregister addressNMIRQ pinWatchdog timer overflowSystem errorReser

Interrupt Controller9-4Interrupt controlregister addressGROUP 93210——GROUP 103210——GROUP 73210x'3400011C——GROUP 83210x'34000

Interrupt Controller9-5Interrupt controlregister addressGROUP 143210———GROUP 153210———GROUP 163210———GROUP 173210———GROUP 183210——

Interrupt Controller9-69.5 Description of RegistersThis interrupt controller includes an interrupt control registers, an interrupt accepted group regi

Interrupt Controller9-7Non-maskable interrupt control registerRegister symbol: G0ICR (NMICR)Address: x'34000100Purpose: This register determines

Interrupt Controller9-8Group n interrupt control register GnICR (n = 2 to 19)Registers G2ICR to G19ICR control level interrupts for groups 2 to 19, re

Interrupt Controller9-9Bit No. Bit name Description11 to 8 IE3 to 0 Group n interrupt enable register• This register is used to specify whether an int

Interrupt Controller9-10Group 2 interrupt control registerRegister symbol: G2ICRAddress: x'34000108Purpose: This register is used to enable group

Interrupt Controller9-11Group 3 interrupt control registerRegister symbol: G3ICRAddress: x'3400010CPurpose: This register is used to enable group

xii12. Watchdog TimerFig. 12-3-1 Block Diagram ...

Interrupt Controller9-12Group 4 interrupt control registerRegister symbol: G4ICRAddress: x'34000110Purpose: This register is used to enable group

Interrupt Controller9-13Group 5 interrupt control registerRegister symbol: G5ICRAddress: x'34000114Purpose: This register is used to enable group

Interrupt Controller9-14Group 6 interrupt control registerRegister symbol: G6ICRAddress: x'34000118Purpose: This register is used to enable group

Interrupt Controller9-15Group 7 interrupt control registerRegister symbol: G7ICRAddress: x'3400011CPurpose:This register is used to enable group

Interrupt Controller9-16Group 8 interrupt control registerRegister symbol: G8ICRAddress: x'34000120Purpose:This register is used to enable group

Interrupt Controller9-17Group 9 interrupt control registerRegister symbol: G9ICRAddress: x'34000124Purpose:This register is used to enable group

Interrupt Controller9-18Group 10 interrupt control registerRegister symbol: G10ICRAddress: x'34000128Purpose:This register is used to enable grou

Interrupt Controller9-19Group 11 interrupt control registerRegister symbol: G11ICRAddress: x'3400012CPurpose:This register is used to enable grou

Interrupt Controller9-20Group 12 interrupt control registerRegister symbol: G12ICRAddress: x'34000130Purpose:This register is used to enable grou

Interrupt Controller9-21Group 13 interrupt control registerRegister symbol: G13ICRAddress: x'34000134Purpose:This register is used to enable grou

xiiiFig. 14-5-2 External Trigger Input Conversion Example(for Channels 0 to 2, One Time Each)...

Interrupt Controller9-22Group 14 interrupt control registerRegister symbol: G14ICRAddress: x'34000138Purpose:This register is used to enable grou

Interrupt Controller9-23Group 15 interrupt control registerRegister symbol: G15ICRAddress: x'3400013CPurpose:This register is used to enable grou

Interrupt Controller9-24Group 16 interrupt control registerRegister symbol: G16ICRAddress: x'34000140Purpose:This register is used to enable grou

Interrupt Controller9-25Group 17 interrupt control registerRegister symbol: G17ICRAddress: x'34000144Purpose:This register is used to enable grou

Interrupt Controller9-26Group 18 interrupt control registerRegister symbol: G18ICRAddress: x'34000148Purpose:This register is used to enable grou

Interrupt Controller9-27Group 19 interrupt control registerRegister symbol: G19ICRAddress: x'3400014CPurpose:This register is used to enable grou

Interrupt Controller9-28Interrupt accepted group registerRegister symbol: IAGRAddress: x'34000200Purpose: This register is used to read the group

Interrupt Controller9-29External interrupt condition specification registerRegister symbol: EXTMDAddress: x'34000280Purpose: This register specif

Interrupt Controller9-309.6 Description of OperationThe following interrupt processing is performed.• Non-maskable interrupts NMIRQ pin interruptWatch

Interrupt Controller9-31[Cautions]1. Maintain external pin interrupt signals for at least 10, 5, or 2.5 SYSCLK cycles when nfr = (MCLK frequency/SYSCL

xiv17. Ordering Mask ROMFig. 17-2-1 ROM Ordering Method 1 ... 17-

Interrupt Controller9-32

10. 8-bit Timers910

8-bit Timers10-210.1 OverviewThis device has 12 reload timers built in.All are down counters that can be used as interval timers and event counters.Ei

8-bit Timers10-310.3 Block DiagramFig. 10-3-1 shows a block diagram for timers 0 to 3.Fig. 10-3-2 shows a block diagram for timers 4 to B.Figures 10-3

8-bit Timers10-4Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B)Output waveform controlTimer n(n = 4, 5, 6, 7, 8, 9, A, B)MatchOutput controlTMnO

8-bit Timers10-5Fig. 10-3-3 8-bit Timer Connection Diagram (Overall)TM0IRQ Timer interrupt 0TMnIN1TMnIN0TMnIN2Block Timer 0 to 3TM0OUTTM0IRQTMnIN5TM

8-bit Timers10-6Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block)TM0IN1TM0IN0TM0IN3TM0IN2TM0CITimer 0TM0OUTTM0IRQTM0COTM0CLKTM0IN5TM0IN4

8-bit Timers10-7TM4IRQ Timer interrupt 4IOCLK/32TM4IN1TM4IN0TM4IN3TM4IN2TM4CITimer 4TM4OUTTM4IRQTM4COTM4CLKTM4IN5TM4IN4TM4IN7TM4IN6TM5IN1TM5IN0TM5IN

8-bit Timers10-8Fig. 10-3-6 8-bit Timer Connection Diagram (Timer 8 to B block)TM8IRQ Timer interrupt 8IOCLK/32TM8IN1TM8IN0TM8IN3TM8IN2TM8CITimer 8T

8-bit Timers10-9Note: Because timers 0 and 8, 1 and 9, 2 and A, and 3 and B share multipurpose output pins, only one of either"timer output"

xvList of Tables1. General SpecificationsTable 1-4-1 Pin Assignments ...

8-bit Timers10-1010.5 Description of RegistersTable 10-5-1 lists the 8-bit timer registers.Table 10-5-1 List of 8-bit Timer Registers (1/2)Address Nam

8-bit Timers10-11Address Name SymbolNumber of bitsInitial value Access sizex'34001034 Timer 4 compare register TM4CMP 8 x'00 8, 16, 32x&apos

8-bit Timers10-12Timer n mode register (n = 0, 1, 2, 3)Register symbol: TMnMDAddress: x'34001000 (n=0), x'34001001 (n=1),x'34001002 (n=

8-bit Timers10-13Timer n mode register (n = 4, 5, 6, 7, 8, 9, A, B)Register symbol: TMnMDAddress: x'34001004 (n=4), x'34001005 (n=5), x&apos

8-bit Timers10-14[Note]When setting TMnCNE to "1", do so while TMnLDE is set to "0".When setting TMnLDE to "1", do so wh

8-bit Timers10-15When using 1/8 IOCLK or 1/32 IOCLK, the prescaler control register (TMPSCNT) must be set.When TMnIO pin input was selected, the risin

8-bit Timers10-16Timer n base register (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)Register symbol: TMnBRAddress: x'34001010 (n = 0), x'34001011

8-bit Timers10-17Timer n compare register (n = 4, 5, 6, 7, 8, 9, A, B)Register symbol: TMnCMPAddress: x'34001034 (n = 4), x'34001035 (n = 5)

8-bit Timers10-18Timer output selection registerRegister symbol: TMOSLAddress: x'34001070Purpose: This register selects the 8-bit timer output si

8-bit Timers10-19Prescaler control registerRegister symbol: TMPSCNTAddress: x'34001071Purpose: This register controls the prescaler operation.Bit

xvi10. 8-bit TimersTable 10-4-1 List of 8-bit Timer Functions ... 10-9T

8-bit Timers10-2010.6 Description of OperationThis section describes the operation of the 8-bit timers.10.6.1 Interval Timers and Timer OutputWhen usi

8-bit Timers10-21(6) Enable the timer counting operation.Once TMnCNE is set to "1" in the TMnMD register, the counting operation starts.Once

8-bit Timers10-22Fig 10-6-1 Interval Timer OperationFig 10-6-2 Interval Timer Operation (When Clock Source = IOCLK)TMnBC valueTMnBR setting valueTMnCN

8-bit Timers10-23Fig. 10-6-3 Interval Timer Operation (Using Prescaler)Timer output(TMnOUT)x'00x'01 TMnBR value TMnBR value-1IOCLKTMnBC valu

8-bit Timers10-2410.6.2 Event CountingWhen using an 8-bit timer for event counting, make the settings according to the procedure described below.When

8-bit Timers10-25[Note]Pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycleswhen (MCLK fr

8-bit Timers10-2610.6.3 Cascaded ConnectionThe 8-bit timers can be cascaded together in the combinations shown in Fig. 10-6-5.Fig. 10-6-5 Cascaded Con

8-bit Timers10-27Make the settings described below when cascading 8-bit timers.(1) Set the timer division ratio.Set the timer division ratio in TMnBR.

8-bit Timers10-28(4) Enable counting operationEnable the counting operation by either one of the following two methods:1) Enable the counting operatio

8-bit Timers10-29 Differences between using a timer as a prescaler and when cascadedThe following explanation of these differences uses the cases wh

xviiTable 15-13-1Port B Configuration ... 15-60Table 15-14-1

8-bit Timers10-30When "cascaded with timer 0" is set, operation is as shown in Fig. 10-6-7. (IOCLK is selected as the clock sourcefor timer

8-bit Timers10-3110.6.4 PWM OutputMake the settings as described below when using an 8-bit timer to output a PWM waveform. (Timers 4 to B)The timers

8-bit Timers10-32Once the counting operation is enabled, the PWM waveform is output and an underflow interrupt request is generated.(Refer to Fig. 10-

8-bit Timers10-33TMnBC valueTimer output(TMnOUT)TMnBR valuex'00IOCLKInterrupt request signal (TMnIRQ)(TMnBR value +1) x IOCLKTMnBR valuex'00

8-bit Timers10-34

11. 16-bit Timers11

16-bit Timers11-211.1 OverviewThis microcontroller has four 16-bit timers built in.Three are reload timers (down-counters) that can be used as interva

16-bit Timers11-311.3 Block DiagramFig. 11-3-1 shows the block diagram for timer 10, and Fig. 11-3-2 shows the block diagram for timers 11to 13.Fig. 1

16-bit Timers11-4Timer n(n = 11, 12, 13)TMnBRTMnBCCK0CK1LDECNETMnMDUnderflowReloadLoadTMnIRQTMnOUTUnderflow interruptTimer outputCounting operation en

16-bit Timers11-5Fig. 11-3-3 16-bit Timer Connection DiagramTimer 10 overflow interruptTM10IOAI/O port blockTM13IOTM13IN1TM13IN0TM13IN4TM13IN2Ti

xviii

16-bit Timers11-6Fig. 11-3-4 shows the block diagram for the timer 10 compare/capture registers.Fig. 11-3-4 Timer 10 Compare/Capture Register Block Di

16-bit Timers11-711.4 FunctionsTable 11-4-1 lists the functions of each 16-bit timer.Table 11-4-1 List of 16-bit Timer FunctionsDown-countingTimerInte

16-bit Timers11-811.5 Description of RegistersTable 11-5-1 lists the 16-bit timer registers.Table 11-5-1 List of 16-bit Timer RegistersAddress Name Sy

16-bit Timers11-9Timer 10 mode registerRegister symbol: TM10MDAddress: x'34001080Purpose: This register controls the operation of timer 10.Bit No

16-bit Timers11-10Bit No. Bit name Description7 TM10TGE External trigger start enable flagEnables/disables timer start by an external trigger.0: Disab

16-bit Timers11-11Timer n mode register (n = 11, 12, 13)Register symbol: TMnMDAddress: x'34001082 (n=11), x'34001084 (n=12), x'34001086

16-bit Timers11-12Timer n base register (n = 11, 12, 13)Register symbol: TMnBRAddress: x'34001092 (n=11), x'34001094 (n=12), x'34001096

16-bit Timers11-13Timer 10 compare/capture A mode registerRegister symbol: TM10MDAAddress: x'340010B0Purpose: This register controls the operatio

16-bit Timers11-14Timer 10 compare/capture B mode registerRegister symbol: TM10MDBAddress: x'340010B1Purpose: This register controls the operatio

16-bit Timers11-15Timer 10 compare/capture A registerRegister symbol: TM10CAAddress: x'340010C0Purpose: This is the timer 10 compare/capture A re

101. General Specifications

16-bit Timers11-16Timer 10 compare/capture B registerRegister symbol: TM10CBAddress: x'340010D0Purpose: This is the timer 10 compare/capture B re

16-bit Timers11-17Prescaler control registerRegister symbol: TMPSCNTAddress: x'34001071Purpose: This register controls prescaler operations.Bit N

16-bit Timers11-1811.6 Description of Operation of Timer 10This section describes the operation of timer 10.Timer 10 includes an up-counter and two co

16-bit Timers11-19Fig. 11-6-1 Compare Register Operation (When Clock Source = IOCLK)11.6.2 Capture Register SettingsIn order to use either the timer 1

16-bit Timers11-20If dual-edge was selected, the capture operation is performed when either a rising or falling edge is input. It is notpossible to d

16-bit Timers11-2111.6.3 Pin Output SettingsTimer 10 can be used to output a variety of waveforms to the TM10IOA and TM10IOB pins.(1) Setting the outp

16-bit Timers11-22Examples of TM10IOA pin output waveforms are shown below. Output for the TM10IOB pin is similar.Fig. 11-6-3 shows the output wavefo

16-bit Timers11-23Fig. 11-6-5 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA" is set.Fig. 11-6-5 Pin Out

16-bit Timers11-2411.6.4 Starting by an External TriggerTimer 10 can be started up by input on the TM10IOB pin. Fig. 11-6-8 illustrates the startup o

16-bit Timers11-25 Procedure for ending operation(1) Disable timer startup by an external trigger.Set TM10TGE in the TM10MD register to "0"

1-2General Specifications1.1 OverviewThe MN1030 Series is a 32-bit microcontroller that maintains the software assets of Matsushita Electronics'

16-bit Timers11-2611.6.5 One-shot OperationIt is possible to stop timer 10 when TM10BC and TM10CA match. Figs. 11-6-9 and 11-6-10 illustrate the oper

16-bit Timers11-27 Procedure for ending operation• When the timer was started by a program (TM10TGE = 0)(1) Stop the counting operation.Set TM10CNE i

16-bit Timers11-2811.6.6 Interval TimerWhen using timer 10 as an interval timer, make the settings according to the procedure described below.This int

16-bit Timers11-29If the value in the TM10CA register is changed while the counting operation is in progress, the value in the bufferis loaded into th

16-bit Timers11-30x'0000 x'0001TM10CA valueTM10CA value-1IOCLKTM10BC valuex'0000 x'0001(TM10CA value + 1) x IOCLKSet value 1Set va

16-bit Timers11-3111.6.7 Event CountingWhen using timer 10 as an event counter, make the settings according to the procedure described below.This even

16-bit Timers11-32Once the counting operation is enabled, TM10BC is incremented each time that the specified edge is input to theTM10IOB pin. Once (v

16-bit Timers11-3311.7 Description of Operation of Timers 11, 12, and 13This section describes the operation of timers 11, 12, and 13.Timers 11, 12, a

16-bit Timers11-34Once the counting operation is enabled, an underflow interrupt request is generated on a regular cycle. In addition,with each inter

16-bit Timers11-35Fig. 11-7-2 Interval Timer Operation (When Clock Source = IOCLK)Fig. 11-7-3 Interval Timer Operation (When Using the Prescaler)x&apo

1-3General SpecificationsHigh-speed/high-performance bus interface Can select either separate address/data buses or multiplex address/data bus• Addr

16-bit Timers11-3611.7.2 Event CountingWhen using timer 11, 12, or 13 as an event counter, make the settings according to the procedure described belo

16-bit Timers11-37[Note]The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLKcycles when (MC

16-bit Timers11-38

12. Watchdog Timer1112

Watchdog Timer12-212.1 OverviewThis microcontroller has a 25-bit binary counter built in that can be used as a 16- to 25-bit watchdog timer.A watchdog

Watchdog Timer12-3OSCIRSTwdovfSQRLevel output/Pulse output selectionOscillation stabilization wait release, interrupt requestReset1/281/2101/2121/2141

Watchdog Timer12-412.4 Description of RegistersTable 12-4-1 lists the watchdog timer registers.Table 12-4-1 List of Watchdog Timer RegistersAddress

Watchdog Timer12-5Watchdog timer control registerRegister symbol: WDCTRAddress: x'34004008Purpose: This register sets the watchdog timer operatio

Watchdog Timer12-63 — When this bit is read, a "0" is returned.4 WDOVF The value of the watchdog timer overflow output.5 WDOVT Watchdog time

Watchdog Timer12-712.5 Description of OperationOscillation stabilization wait operationThe watchdog timer operates as an oscillation stabilization wai

If you have any inquiries or questions about this book or our semiconductors, please contact one of our salesoffices listed at the back of this book.(

1-4General SpecificationsClock and system controllerA/D10-bit4 inputsSIFUART x 1multipurpose x 1synchronous system x 2ROM128 KB(flash memory 256 KB)D

Watchdog Timer12-8Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP ModeInterruptStop mode release request (external pin interrupt)Overflow

Watchdog Timer12-9Watchdog operationIf the WDCNE flag is set to "1" and the watchdog operation is enabled, a non-maskable interrupt is gener

Watchdog Timer12-10

13. Serial Interface13

Serial Interface13-213.1 OverviewThis microcontroller has three types of internal serial interfaces. One is a general-purpose serial interface for wh

Serial Interface13-313.2 General-purpose serial interface13.2.1 FeaturesSerial interface 0 is a general-purpose serial interface for which clock sync

Serial Interface13-4<UART mode>• Parity None, 0 fixed, 1 fixed, even, odd• Character length 7 bits, 8 bits• Transmission and reception bit seque

Serial Interface13-513.2.2 Block Diagram of General-Purpose Serial InterfaceFig 13-2-1 shows the block diagram for the general-purpose serial interfac

Serial Interface13-613.2.3 Description of Registers for the General-Purpose Serial InterfaceThe general-purpose serial interface includes the register

Serial Interface13-76 SC0PB2 Parity bit selection (MSB)000: None001, 010, 011: Setting prohibited100: 0 fixed101: 1 fixed110: Even (even number o

1-5General SpecificationsFig. 1-4-1 Pin Assignments Diagram* "VDD2" in the case of the MN103001G, "VPP" in the case of the MN1

Serial Interface13-8Serial 0 interrupt mode registerRegister symbol: SC0ICRAddress: x'34000804Purpose: This register selects the sources for tran

Serial Interface13-9Serial 0 reception bufferRegister symbol: SC0RXBAddress: x'34000809Purpose: This register reads in the reception data of seri

Serial Interface13-1013.2.4 Description of Operation<Clock synchronous mode> Clock synchronous mode connectionTwo different connection methods

Serial Interface13-11 Clock synchronous mode timing<Transmission>• One-byte transfer with 8-bit data length and parity onFig. 13-2-3 Timing C

Serial Interface13-12<Reception>• One-byte transfer with 8-bit data length and parity onFig. 13-2-5 Timing Chart (3)• Two-byte transfer with 8

Serial Interface13-13 When a reception error is generated• Transfer in clock synchronous mode with 8-bit data length, parity on.Fig. 13-2-7 Timing

Serial Interface13-14SBOSBISBTSBOSBISBTSBOSBISBOSBISBT SBTReceptionTransmissionTransmission/receptionTransmission/receptionExternalclockExternalclockB

Serial Interface13-15Table 13-2-2 Bit rates (1) (When IOCLK = 15 MHz)Bit rate (bit/s)When cascaded When using prescalersTimer division ratio Bit rat

Serial Interface13-16 UART mode timing<Transmission>• Transfer with 8-bit data length, parity on, and 1 stop bitFig. 13-2-9 Timing Chart (6)•

Serial Interface13-17<Reception>• Transfer with 8-bit data length, parity on, and 1 stop bitFig. 13-2-11 Timing Chart (8)• Two-byte transfer w

1-6General SpecificationsTable 1-4-1 Pin Assignments• Pins for which two or more names are shown are multipurpose pins.* "VDD2" in the ca

Serial Interface13-18 When a reception error is generated• Transfer in UART mode with 8-bit data length, parity on, and 1 stop bitFig. 13-2-13 Timi

Serial Interface13-19<I2C mode> I2C mode connectionIt is possible to connect a device that is capable of slave transmission and slave reception

Serial Interface13-20 I2C mode transmission/receptionThe transmission/reception procedure in I2C mode is described below.(Refer to Fig. 13-2-15.)• M

Serial Interface13-21• Perform data transmission/reception (B) according to the procedure described below:(1) Ack setting"Ack" is represent

Serial Interface13-22If the above procedures do not satisfy the AC timing of the device that is connected, send the stop sequenceaccording to the proc

Serial Interface13-23• Resend the start sequence (D) according to the procedure described below. (Refer to Fig. 13-2-16.)(1) SBO pin settingSet the

Serial Interface13-2413.3 Clock Synchronous Serial Interface13.3.1 FeaturesSerial interfaces 1 and 2 are clock synchronous serial interfaces. Their f

Serial Interface13-2513.3.2 Block Diagram of Clock Synchronous Serial InterfaceFig 13-3-1 shows the block diagram for the clock synchronous serial int

Serial Interface13-2613.3.3 Description of Registers for the Clock Synchronous Serial InterfaceThe clock synchronous serial interfaces include the reg

Serial Interface13-27Serial n control register (n = 1, 2)Register symbol: SCnCTRAddress: x'34000810 (n =1), x'34000820 (n =2)Purpose: This r

1-7General Specifications1.4.2 Pin FunctionsTable 1-4-2 shows the function of each pin of this microcontroller.Table 1-4-2 Pin Function Table (1/2)Ca

Serial Interface13-28Bit No. Bit name Description8 SCnTOE SBTn pin output control0: When the internal clock is selected, the SBTn pin is an output onl

Serial Interface13-29Serial n interrupt mode register (n = 1, 2)Register symbol: SCnICRAddress: x'34000814 (n = 1), x'34000824 (n = 2)Purpos

Serial Interface13-30Serial n transmission buffer (n = 1, 2)Register symbol SCnTXBAddress: x'34000818 (n=1), x'34000828 (n=2)Purpose: This r

Serial Interface13-31Serial n status register (n=1,2)Register symbol: SCnSTRAddress: x'3400081C (n=1), x'3400082C (n=2)Purpose: This registe

Serial Interface13-32SBOSBISBTTransmissionSBOSBISBTReceptionSBOSBISBTTransmission/receptionSBOSBISBTTransmission/receptionUnidirectional transfer Bi-d

Serial Interface13-33 Clock synchronous serial interface timing<Transmission>• One-byte transfer with 8-bit data length and parity offFig. 13-3

Serial Interface13-34<Reception>• One-byte transfer with 7-bit data length and parity onFig. 13-3-5 Timing Chart (15)• Two-byte transfer with

Serial Interface13-35 When a reception error is generated• Transfer with 7-bit data length, parity onFig. 13-3-7 Timing Chart (17)When "recept

Serial Interface13-3613.4 Universal Asynchronous Receiver-Transceiver Serial Interface13.4.1 FeaturesSerial interface 3 is a UART serial interface. I

Serial Interface13-3713.4.2 Block Diagram of UART Serial InterfaceFig 13-4-1 shows the block diagram for the UART serial interface sections.Fig. 13-4-

1-8General SpecificationsTable 1-4-2 Pin Function Table (2/2)Category Pin nameInput/ NumberPin FunctionOutput of pinsReset RST I 1 Reset inputInterru

Serial Interface13-3813.4.3 Description of Registers for the UART Serial InterfaceThe UART serial interface includes the registers listed in Table 13-

Serial Interface13-39Serial 3 control registerRegister symbol: SC3CTRAddress: x'34000830Purpose: This register sets the serial interface 3 operat

Serial Interface13-40Bit No. Bit name Description8 SC3TWE Transmission interrupt enable0: Interrupt disable1: Interrupt enable9 SC3OD Transmission and

Serial Interface13-41Serial 3 interrupt mode registerRegister symbol: SC3ICRAddress: x'34000834Purpose: This register selects the sources for tra

Serial Interface13-42Serial 3 transmission bufferRegister symbol: SC3TXBAddress: x'34000838Purpose: This register writes the transmission data of

Serial Interface13-43Serial 3 status registerRegister symbol: SC3STRAddress: x'3400083CPurpose: This register indicates the status of serial inte

Serial Interface13-44Serial 3 timer registerRegister symbol: SC3TIMAddress: x'3400083DPurpose: This register sets the timer that is used for inte

Serial Interface13-4513.4.4 Description of Operation UART Serial Interface connectionTwo different connection methods are possible, one for unidirect

Serial Interface13-46Division ratio 1 = INT (IOCLK frequency / bit rate/127) + 1Division ratio 2 = INT (IOCLK frequency / bit rate/division ratio 1 +

Serial Interface13-47Table 13-4-3 Bit Rates (2) (When IOCLK = 12 MHz)Bit rate (bit/s) Division ratio 1 Division ratio 2 Bit rate error230 400 1 52 0

2. CPU2

Serial Interface13-48[Notes on Usage]1 Set SC3CTR before setting the other registers, and do not change the setting while transmitting or receiving, o

Serial Interface13-49 UART Serial Interface timing<Transmission>• Transfer with 7-bit data length, parity off, and 2 stop bitFig. 13-4-3 Timi

Serial Interface13-50<Reception>• Transfer with 7-bit data length, parity on, and 2 stop bitFig. 13-4-5 Timing Chart (20)• Two-byte transfer w

Serial Interface13-51 When a reception error is generated• Transfer with 7-bit data length, parity on, and 2 stop bitFig. 13-4-7 Timing Chart (22)W

Serial Interface13-52

14. A/D Converter14

A/D Converter14-2AN0AN1AN2AN3S/HAD3BUFAD2BUFAD1BUFAD0BUFVREFHADTRG10-bit sequentialcomparison A/D converterSelector14.1 OverviewThe A/D converter is a

A/D Converter14-314.2 Features• S/H Built in• Conversion accuracy10 bits ± 5 LSB (Linearity error)The value of VREFH divided into 1024 steps is stored

A/D Converter14-414.3 Block DiagramFig. 14-3-1 The Block Diagram of A/D ConverterVREFH1248163264128256512ADCTRADnBUFINCIOCLK1AN0AN1AN2AN3ADTRGSelect

A/D Converter14-514.4 Description of RegistersTable 14-4-1 lists the registers for this A/D converter.Table 14-4-1 A/D Register ListAddress Name Sym

2-2CPU2.1 Basic Specifications of CPU• Structure Load/store architectureData/Address/SP Registers x 9(Data registers: 32-bit x 4, Address registers: 3

A/D Converter14-67 ADEN Conversion start/execution flag(conversion can be started by writing a "1" to this flag)0: Conversion stopped1: Conv

A/D Converter14-714.5 Description of Operation Operating mode selection(1) Any one channel/one-time conversionIf "any one channel/one-time conve

A/D Converter14-8(2) Multiple channels/one-time conversion for each channelIf "multiple channels/one-time conversion for each channel" is se

A/D Converter14-9(3) Any one channel/continuous conversionIf "any one channel/continuous conversion" is selected as the operating mode (ADMD

A/D Converter14-10(4) Multiple channels/continuous conversionIf "multiple channels/continuous conversion" is selected as the operating mode

A/D Converter14-11S/H bp9 bp8 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0S/H bp9 bp8 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 S/H16 (= 12 +4) cyclesADEN flagConversion ref

A/D Converter14-12[Notes]If a falling edge is input to the ADTRG pin before the conversion start trigger selection (ADST1 to 0) isswitched to "ex

15. I/O Ports15

I/O Ports15-215.1 OverviewThe MN103001G and MN1030F01K have a total of 13 internal I/O ports: 0 to 9, A, B and C. These portscan all be accessed by

I/O Ports15-3Port 7 (P7)This port is also used for address bus signal A23; DRAM RAS signals RAS2 and RAS1; and chipselect signals CS3 to CS0.Port 8 (P

2-3CPU2.2 Block DiagramThe block diagram for this microcontroller, focusing on the CPU, is shown below.Fig. 2-2-1 CPU Core Block DiagramInstruction

I/O Ports15-4The I/O ports are provided with the registers listed in Table 15-1-1.Table 15-1-1 List of Registers (1/2)Address Name SymbolNumber of b

I/O Ports15-5Table 15-1-1 List of Registers (2/2)Address Name SymbolNumber of bitsInitial value Access sizex'36008081 Port 1 pin register P1IN 8

I/O Ports15-615.2 Port 015.2.1 Block DiagramFig. 15-2-1 and Fig 15-2-2 show block diagrams for port 0.Fig. 15-2-1 Port 0 Block Diagram (P02)Internal

I/O Ports15-7Fig. 15-2-2 Port 0 Block Diagram (P01, P00)15.2.2 Register DescriptionsPort 0 is a general-purpose output port that is also used for addr

I/O Ports15-8Port 0 output mode registerRegister symbol: P0MDAddress: x'36008020Purpose: This register selects the content output on the port 0

I/O Ports15-915.2.3 Pin ConfigurationsTable 15-2-1 shows the pin configurations for port 0.Table 15-2-1 Port 0 ConfigurationPort Pin P0n P0nMD = &quo

I/O Ports15-1015.3 Port 115.3.1 Block DiagramFigs. 15-3-1 and 15-3-2 show block diagrams for port 1.Fig. 15-3-1 Port 1 Block Diagram (P17 to P12)Int

I/O Ports15-11Fig. 15-3-2 Port 1 Block Diagram (P11, and P10)Internal data busMPXP1OUTP1nOD1(n=1),D0(n=0)P1MP1MDP1DIRP1nDP... Represents one bit of e

I/O Ports15-1215.3.2 Register DescriptionsPort 1 is a general-purpose input/output port that is also used for data bus signals D[7:0], address strobe

I/O Ports15-13Port 1 input/output control registerRegister symbol: P1DIRAddress: x'36008061Purpose: This register sets the port 1 pins for input

2-4CPU31D0D1D2D3031A0A1A2A3031SP031PC031MDR015PSW031LIR031LAR0Data RegisterAddress RegisterStack PointerProgram CounterMultiply/Divide RegisterProcess

I/O Ports15-1415.3.3 Pin ConfigurationsTable 15-3-1 shows the pin configurations for port 1.Table 15-3-1 Port 1 ConfigurationPort Pin P1n P1M = &quo

I/O Ports15-1515.4 Port 215.4.1 Block DiagramFigs. 15-4-1 shows a block diagrams for port 2.Fig. 15-4-1 Port 2 Block Diagram (P27 to P20)Internal dat

I/O Ports15-1615.4.2 Register DescriptionsPort 2 is a general-purpose input/output port that is also used for data bus signals D[15:8].Each register

I/O Ports15-17Port 2 input/output control registerRegister symbol: P2DIRAddress: x'36008064Purpose: This register sets the port 2 pins for input

I/O Ports15-1815.4.3 Pin ConfigurationsTable 15-4-1 shows the pin configurations for port 2.Table 15-4-1 Port 2 ConfigurationPort Pin P2n P2M = &quo

I/O Ports15-1915.5 Port 315.5.1 Block DiagramFig. 15-5-1 shows a block diagram for port 3.Fig. 15-5-1 Port 3 Block Diagram (P30)Internal data busMPXP

I/O Ports15-2015.5.2 Register DescriptionsPort 3 is a general-purpose input/output port that is also used for the bus grant signal BG.Each register f

I/O Ports15-21Port 3 output mode registerRegister symbol: P3MDAddress: x'36008025Purpose: This register selects the content output on the port 3

I/O Ports15-2215.6 Port 415.6.1 Block DiagramFigs. 15-6-1 to 15-6-4 show block diagrams for port 4.Fig. 15-6-1 Port 4 Block Diagram (P45 and P43)P4n

I/O Ports15-23Fig. 15-6-2 Port 4 Block Diagram (P44)Internal data busP44P4OUTP44IP4INP44MP4MDP4DIRP44DP44OP... Represents one bit of each register.P4

2-5CPU0Z1500S1 S0 IE IM2 IM10000IM0VCNFig. 2-3-2 Processor Status Word Data Register (32-bit x 4)This register can be used generally for all operat

I/O Ports15-24Fig. 15-6-3 Port 4 Block Diagram (P42, P40)Fig. 15-6-4 Port 4 Block Diagram (P41)Internal data busP4n(n=2,0)P4OUTP4DIRP4nDP4nOP... Re

I/O Ports15-2515.6.2 Register DescriptionsPort 4 is a general-purpose input/output port that is also used for serial interface input/output signals SB

I/O Ports15-26Port 4 input/output control registerRegister symbol: P4DIRAddress: x'36008068Purpose: This register sets the port 4 pins for input

I/O Ports15-27Port 4 dedicated output control registerRegister symbol: P4SSAddress: x'36008048Purpose: Along with P4MD, this register selects the

I/O Ports15-2815.6.3 Pin ConfigurationsTable 15-6-1 shows the pin configurations for port 4.Table 15-6-1 Port 4 ConfigurationPort Pin P4n P4nM = &qu

I/O Ports15-2915.7 Port 515.7.1 Block DiagramFigs. 15-7-1 to 15-7-5 show block diagrams for port 5.Fig. 15-7-1 Port 5 Block Diagram (P55)Internal dat

I/O Ports15-30Fig. 15-7-2 Port 5 Block Diagram (P54)Internal data busP5OUTP54OTM12IOMPXP54MPXP... Represents one bit of each register.P54IP5INTM12IO

I/O Ports15-31Fig. 15-7-3 Port 5 Block Diagram (P53)Internal data busP5OUTP53OTM11IOMPXP53MPXP... Represents one bit of each register.P53IP5INTM11IO/

I/O Ports15-32Fig. 15-7-4 Port 5 Block Diagram (P52, P50)P5n(n=2,0)Internal data busP5OUTP5DIRP5nDP5nOP... Represents one bit of each register.MPXMP

I/O Ports15-33Fig. 15-7-5 Port 5 Block Diagram (P51)Internal data busTM1IOP5OUTP51OMPXTM1IO/SBI2P51P... Represents one bit of each register.P51IP5INP

2-6CPUZ: Zero FlagThis flag is set when an operation result is all zeroes, and is cleared by any other result. This flag isalso cleared by a reset.N:

I/O Ports15-3415.7.2 Register DescriptionsPort 5 is a general-purpose input/output port that is also used for the serial interface input/output signa

I/O Ports15-35Port 5 input/output control registerRegister symbol: P5DIRAddress: x'36008069Purpose: This register sets the port 5 pins for input

I/O Ports15-36Port 5 dedicated output control registerRegister symbol: P5SSAddress: x'36008049Purpose: Along with P5MD, this register selects th

I/O Ports15-3715.7.3 Pin ConfigurationsTable 15-7-1 shows the pin configurations for port 5.Table 15-7-1 Port 5 ConfigurationPort Pin P5n P5nM = &quo

I/O Ports15-3815.8 Port 615.8.1 Block DiagramFigs. 15-8-1 shows the block diagrams for port 6.Fig. 15-8-1 Port 6 Block Diagram (P63 to P60)Internal

I/O Ports15-3915.8.2 Register DescriptionsPort 6 is a general-purpose input/output port that is also used for external interrupt inputs IRQ3 to IRQ0;

I/O Ports15-40Port 6 output mode registerRegister symbol: P6MDAddress: x'3600802CPurpose: This register selects the content output on the port 6

I/O Ports15-4115.9 Port 715.9.1 Block DiagramFig. 15-9-1 and Fig. 15-9-2 show block diagrams for port 7.Fig. 15-9-1 Port 7 Block Diagram (P73)Fig. 15

I/O Ports15-4215.9.2 Register DescriptionsPort 7 is a general-purpose output port that is also used for address bus signal A23, DRAM RAS signals RAS2

I/O Ports15-43Port 7 dedicated output control registerRegister symbol: P7SSAddress: x'3600804DPurpose: This register selects the content output o

2-7CPU2.3.2 Control RegistersThis microcontroller uses the memory-mapped-I/O method and allocates the peripheral circuit registers to theinternal I/O

I/O Ports15-4415.9.3 Pin ConfigurationsTable 15-9-1 shows the pin configurations for port 7.Table 15-9-1 Port 7 ConfigurationPort Pin P7n P7nM = &qu

I/O Ports15-4515.10 Port 815.10.1 Block DiagramFigs. 15-10-1 shows the block diagrams for port 8.Fig. 15-10-1 Port 8 Block Diagram (P83 to P80)Intern

I/O Ports15-4615.10.2 Register DescriptionsPort 8 is a general-purpose input port that is also used for analog signal inputs AN3 to AN0 and externali

I/O Ports15-4715.10.3 Pin ConfigurationsTable 15-10-1 shows the pin configurations for port 8.Table 15-10-1 Port 8 ConfigurationPortPin No.P8n P8nA =

I/O Ports15-4815.11 Port 915.11.1 Block DiagramFig. 15-11-1 to Fig. 15-11-4 show block diagrams for port 9.Fig. 15-11-1 Port 9 Block Diagram (P97)Fi

I/O Ports15-49Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90)Fig. 15-11-4 Port 9 Block Diagram (P94, P93, P92)Internal data busP... Represents one

I/O Ports15-5015.11.2 Register DescriptionsPort 9 is also used for extension mode setting signals EXMOD1 and EXMOD0; memory write signals WE1and WE0;

I/O Ports15-51Port 9 output mode registerRegister symbol: P9MDAddress: x'36008031Purpose: This register selects the content output on the port 9

I/O Ports15-5215.11.3 Pin ConfigurationsTable 15-11-1 shows the pin configurations for port 9.Table 15-11-1 Port 9 ConfigurationPort Pin P9n P9nM =

I/O Ports15-5315.12 Port A15.12.1 Block DiagramFig. 15-12-1 shows a block diagram for port A.Fig. 15-12-1 Port A Block Diagram (PA7 to PA0)Internal d

2-8CPUInterrupt Vector Register (IVARn)The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt

I/O Ports15-5415.12.2 Register DescriptionsPort A is a general-purpose input/output port that is also used for address bus signals A[7:0], and addres

I/O Ports15-55Port A input/output control registerRegister symbol: PADIRAddress: x'36008074Purpose: This register sets the port A pins for input

I/O Ports15-5615.12.3 Pin ConfigurationsTable 15-12-1 shows the pin configurations for port A.Table 15-12-1 Port A ConfigurationPort Pin PAn PAM = &

I/O Ports15-5715.13 Port B15.13.1 Block DiagramFig. 15-13-1 shows a block diagram for port B.Fig. 15-13-1 Port B Block Diagram (PB7 to PB0)Internal d

I/O Ports15-5815.13.2 Register DescriptionsPort B is a general-purpose input/output port that is also used for address bus signals A[15:8], and addre

I/O Ports15-59Port B input/output control registerRegister symbol: PBDIRAddress: x'36008075Purpose: This register sets the port B pins for input

I/O Ports15-6015.13.3 Pin ConfigurationsTable 15-13-1 shows the pin configurations for port B.Table 15-13-1 Port B ConfigurationPort Pin PBn PBM = &

I/O Ports15-6115.14 Port C15.14.1 Block DiagramFig. 15-14-1 shows a block diagram for port C.Fig. 15-14-1 Port C Block Diagram (PC3 to PC0)Internal d

I/O Ports15-6215.14.2 Register DescriptionsPort C is a general-purpose output port that is also used for address bus signals A[19:16].Each register f

I/O Ports15-6315.14.3 Pin ConfigurationsTable 15-14-1 shows the pin configurations for port C.Table 15-14-1 Port C ConfigurationPort Pin No. PCn PCnM

2-9CPUCPU Mode Register (CPUM)The CPU mode register (CPUM) sets the clock operating mode for the CPU and peripheral blocks. This register isallocated

I/O Ports15-6415.15 Treatment of Unused PinsUnused pins should be treated as shown in Table 15-15-1 below.Table 15-15-1 Treatment of Unused PinsPin

16. Internal Flash Memory16

Internal Flash Memory16-216.1 OverviewThe MN1030F01K has 256 KB of internal flash memory for use as instruction memory in place of instructionROM. Us

Internal Flash Memory16-316.4 Flash Memory Overwrite Mode and SettingsThere are two flash memory overwrite modes: flash memory mode and on-board writ

Internal Flash Memory16-416.5 Flash Memory Mode16.5.1 Description of External PinsFig. 16-5-1 and Table 16-5-1 show the pin assignments for the MN1030

Internal Flash Memory16-5Table 16-5-1 MN1030F01K Pin AssignmentsI: Input; O: Output; I/O: Input/output; H: High level input; L: Low level inputPinN

Internal Flash Memory16-6Table 16-5-2 lists the functions of the external pins in flash memory mode.Table 16-5-2 Pin FunctionsWhen first applying po

Internal Flash Memory16-716.5.2 Erasure BlocksThe flash memory is partitioned into 32 8 KB erasure blocks. Fig. 16-5-2 shows the configuration of th

Internal Flash Memory16-816.6 On-board Write ModeIn on-board write mode, flash memory is overwritten by manipulating the control registers through sof

1717. Ordering Mask ROM

2-10CPUAm/An031PC031031031(32-bit address)031(32-bit address)031(32-bit address)031(32-bit address)031Register directImmediate value Dm / DnAm / Anim

Ordering Mask ROM17-217.1 OverviewThis chapter describes the procedure for ordering mask ROM. This chapter also describes the difference inprogrammin

Ordering Mask ROM17-3Fig. 17-2-2 ROM Ordering Method 2x'40000000x'40000000x'40002000User programUser programLoader program8 KBx'

Ordering Mask ROM17-4

Appendix

AppendixAppendix-2Appendix A. Register Map List0IVAR0MEMCTR0BMEMCTR1BMEMCTR2BMEMCTR3Bx'3200004Xx'3200400Xx'3400010Xx'3400011Xx&ap

AppendixAppendix-3TMOSLTM10MDATM0MDTM0BRTM0BCSC1CTRSC0CTRx'3400080Xx'3400082Xx'3400083Xx'3400081XSC3CTRSC2CTRSC0ICRSC1ICRSC2ICRSC3

AppendixAppendix-4FEDCBA9876543210x'3600800XAddressI/O portP1OUTP9OUTP0MDP1MDP8ADP0SSP1DIRP8INP9INP9DIRx'3600801Xx'3600802Xx'36008

AppendixAppendix-5Appendix B. Instruction SetList of Instructions ( Code Length, Execution Cycle*)Execution cycle is defined under the following cond

AppendixAppendix-6Instruction Source Destination Format RemarksMOVBU MOVBU (Am) Dn D0 2 1MOVBU (d8,Am) Dn D1 3 1MOVBU (d16,Am) Dn D2 4 1MOVBU (d32,Am)

AppendixAppendix-7Instruction Source Destination Format RemarksMOVM 4 Registers specified by regs = 48 Registers specified by regs = 79 Registers spec

2-11CPU2.4.2 Data TypesData types can be processed in the four types of bit, byte, halfword and word data. Byte data, halfword data andword data can b

AppendixAppendix-8* Varies according to the state of the instruction buffer.Code lengthExecution CycleInstruction Source Destination Format RemarksAND

AppendixAppendix-9Instruction Source Destination Format RemarksSETLB SETLB S0 1 1JMP JMP (An) D0 2 3JMP (d16,PC) S2 3 2JMP (d32,PC) S4 5 4CALL CALL (d

AppendixAppendix-10List of Extension Instructions ( Code Length, Execution Cycle)Instruction Source Destination Format Code length Execution cycle Rem

AppendixAppendix-11Appendix C. Memory Connection ExampleFig. C-1 shows a connection example for the memory configuration described below.Block 0: 16-

AppendixAppendix-12Appendix D. Pins and Their Operating Statuses upon ResetIn the address/data separate modePinNo.Pin nameOperatingstatus1 A19 L 26 PV

AppendixAppendix-13Note 1) Hi-Z: High impedanceH: High level outputL: Low level outputPull-up: Pull-upInput: Input an appropriate value.Note 2) The pi

AppendixAppendix-14Appendix E. Package OutlineThe package outline and dimensions of this microcontroller are shown below.Package code : LQFP100-P-141

ErrorsPageCorrectionsPage- i -P.1-3P.1-8P.2-9P.2-13P.2-14P.2-15P.2-15P.2-17P.2-18P.2-18P.2-18P.2-19P.2-19P.2-20P.3-5P.3-7P.1-3P.1-8P.2-9P.2-13P.2-14P.

ErrorsPageCorrectionsPage- ii -P.3-8P.3-9P.3-10P.3-21P.3-22P.3-23P.3-23P.3-24P.3-25P.3-25P.3-26P.3-26P.3-27P.3-29(Following sentences are added to [Pr

ErrorsPageCorrectionsPage- iii - (Omit)Note that operation is not assured when attempting to accessunmounted space.Note that operation is not assured

2-12CPU2.4.3 Instruction SetThe instruction set has a simple organization, and features the generation of compact and optimized code through aC compil

ErrorsPageCorrectionsPage- iv -P.6-3P.6-3P.6-4P.8-5P.8-11,P.8-15P.8-15,P.8-20P.8-35P.8-35P.8-36P.8-41P.6-3P.6-3P.6-4P.8-5P.8-11,P.8-15P.8-15,P.8-20P.8

ErrorsPageCorrectionsPage- v -P.8-42P.8-43toP.8-44P.8-48P.8-49P.8-49P.8-50P.8-56P.8-57P.8-58P.8-59-P.8-42P.8-43toP.8-44P.8-48P.8-49P.8-49P.8-50P.8-56P

ErrorsPageCorrectionsPage- vi -P.9-3P.9-7P.9-7P.9-7P.9-7P.9-7P.9-8P.9-30P.9-30P.11-6P.12-2P.12-2P.12-2(In fig. 9-4-1.)(Register's purpose)This re

ErrorsPageCorrectionsPage- vii -(In the table of Example.)(The 2nd line from the bottom.)An oscillation stabilization wait time of at least 14 ms is

(All of the series name in this manual is changed as shown below: • "MN10300 Series" is changed the name into "MN1030 Series".

MN103001G/F01KLSI User's ManualFebruary, 2002 5th EditionIssued by Matsushita Electric Industrial Co., Ltd.© Matsushita Electric Industrial Co.,

Semiconductor Company, Matsushita Electric Industrial Co., Ltd.Nagaokakyo, Kyoto 617-8520, JapanTel: (075) 951-8151http://www.panasonic.co.jp/semicon/

2-13CPU• Bit instructionsBTST Bit TestBSET Test and set (processing unit: byte)BCLR Test and clear (processing unit: byte)• Shift instructionsASR Shif

2-14CPU2.5 Interrupts2.5.1 Overview of InterruptsThe most important key to real-time control is the ability to shift quickly to interrupt handler proc

2-15CPU0ID1501413121110987654321000000 000000ID1501413121110987654321LV IE IRG0ICR (NMICR)GnICR (n = 2 to 19)2.5.2 Registers[Flags in the PSW] (CPU)In

2. CPU3. Extension Instruction Specifications4. Memory Modes5. Operating Mode6. Clock Generator7. Internal Memory8. Bus Controller (BC)9. Interrupt Co

2-16CPULV2 to LV0 (Interrupt Priority Level) R/W• This 3-bit field sets the interrupt priority level. When the interrupt priority level set in LV2 to

2-17CPU[Interrupt Accept Group Register (IAGR)] R halfword/byte accessDuring a register read, the interrupt accept group register (IAGR) indicates the

2-18CPU2.5.3 Interrupt TypesThe three types of interrupts are listed below:[Reset interrupt]The reset interrupt is the interrupt with the highest prio

2-19CPU[Level interrupts]Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable (IE) andinterrup

2-20CPU(Example of pre-processing by the interrupt handler)1. The registers are saved.The saved registers are those used by the interrupt handler.2. T

2-21CPUAn even higher interrupt response speed can be realized by assigning only one factor or only a few factors to asingle interrupt level.Fig. 2-5-

2-22CPU[Stack Frame]When an interrupt is accepted, a stack frame is allocated and the total 6 bytes of information in the PC and PSW aresaved in order

3. Extension Instruction Specifications3

Extension Instruction Specifications3-23.1 Operation Extension FunctionThe MN1030 series 32-bit microcontrollers are provided with 32 extension instru

Extension Instruction Specifications3-33.2 Extension Instructions3.2.1 Explanation of NotationsThe notations used to describe instruction manual are s

Extension Instruction Specifications3-4Multiply RegisterMultiply & AccumulateRegister (Higher)Multiply & AccumulateRegister (Lower)Multiply &a

Extension Instruction Specifications3-53.2.3 Extension Instruction DetailsPUTX (Register transfer instruction for high-speed multiplication: Load)[Ins

Extension Instruction Specifications3-6PUTCX (Register transfer instruction for multiply-and-accumulate operation: Load)[Instruction Format (Macro Nam

Extension Instruction Specifications3-7GETX (Register transfer instruction for high-speed multiplication: Store)[Instruction Format (Macro Name)]GETX

Extension Instruction Specifications3-8GETCHX (Register high-order 32-bit transfer instruction for multiply-and-accumulate operation: Store)[Instructi

Extension Instruction Specifications3-9GETCLX (Register low-order 32-bit transfer instruction for multiply-and-accumulate operation: Store)[Instructio

Extension Instruction Specifications3-10CLRMAC (Register clear instruction for multiply-and-accumulate operation)[Instruction Format (Macro Name)]CLRM

Extension Instruction Specifications3-11MULQ (Signed high-speed multiplication instruction: between registers)[Instruction Format (Macro Name)]MULQ D

Extension Instruction Specifications3-12MULQI (Signed high-speed multiplication instruction: between immediate value and register)[Instruction Format

Extension Instruction Specifications3-13MULQU (Unsigned high-speed multiplication instruction: between registers)[Instruction Format (Macro Name)]MULQ

14. A/D Converter15. I/O Ports16. Internal Flash Memory17. Ordering Mask ROMAppendix14151617

Extension Instruction Specifications3-14MULQIU (Unsigned high-speed multiplication instruction: between immediate value and register)[Instruction Form

Extension Instruction Specifications3-15MAC (Signed multiply-and-accumulate operation instruction: between registers)[Instruction Format (Macro Name)]

Extension Instruction Specifications3-16MACH (Signed half word data multiply-and-accumulate operation instruction: between registers)[Instruction Form

Extension Instruction Specifications3-17MACB (Signed byte data multiply-and-accumulate operation instruction: between registers)[Instruction Format (M

Extension Instruction Specifications3-18MACU (Unsigned multiply-and-accumulate operation instruction: between registers)[Instruction Format (Macro Nam

Extension Instruction Specifications3-19MACHU (Unsigned half word data multiply-and-accumulate operation instruction: between registers)[Instruction F

Extension Instruction Specifications3-20MACBU (Unsigned byte data multiply-and-accumulate operation instruction: between registers)[Instruction Format

Extension Instruction Specifications3-21SAT16 (16-bit saturation operation instruction)[Instruction Format (Macro Name)]SAT16 Dm, Dn[Assembler Mnemon

Extension Instruction Specifications3-22SAT24 (24-bit saturation operation instruction)[Instruction Format (Macro Name)]SAT24 Dm, Dn[Assembler Mnemon

Extension Instruction Specifications3-23MCST (Multiply-and-accumulate operation results 8-, 16-, 32-bit saturation operation instruction)[Instruction

Extension Instruction Specifications3-24[Flag Changes]When multiply-and-accumulate operation overflow was not detected (MCVF = 0)Flag Change Condition

Extension Instruction Specifications3-25MCST9 (Multiply-and-accumulate operation results 9-bit saturation operation instruction/positive valueconversi

Extension Instruction Specifications3-26MCST48 (Multiply-and-accumulate operation results 48-bit saturation operation instruction)[Instruction Format

Extension Instruction Specifications3-27Bit 31 Bit 010000000000000000Dn before execution Dn after executionSearch rangeSearch directionMSB LSBBSCH (Bi

Extension Instruction Specifications3-28SWAP (Data swapping instruction that swaps bytes [high-order to low-order and vice versa] in four-byte data)[I

Extension Instruction Specifications3-29[Flag Changes]Flag Change ConditionV * UndefinedC * UndefinedN * UndefinedZ * Undefined[Programming Cautions]P

Extension Instruction Specifications3-30Bit 31Bit 0MSBLSBDm before executionDn after executionDm[31:24]Dm[23:16] Dm[15:8] Dm[7:0]Bit 31Bit 0MSBLSBDm[7

Extension Instruction Specifications3-31Multiply-and-accumulateinstruction *3MCRH, MCRLaccess instruction *4MCRH, MCRLaccess instruction *4Multiply-an

Extension Instruction Specifications3-32(a) Note on the description of word/half-word data multiply-and-accumulate instructions and multiply-and-accum

Extension Instruction Specifications3-33(b) Note on the description of word/half-word data multiply-and-accumulate instructions and MCRH, MCRLaccess i

Table of Contents/List of Figures and Tables0

Extension Instruction Specifications3-34(c) Note on the description of byte data multiply-and-accumulate instructions and MCRH, MCRL access instructio

Extension Instruction Specifications3-35(d) Note on the description of multiply-and-accumulate instructions and multiply-and-accumulate instructions o

Extension Instruction Specifications3-36(e) Note on the description of memory access and multiply-and-accumulate instruction or high-speed multiplicat

Extension Instruction Specifications3-37If a stack area is in the internal RAM, any error making potential condition shown on the following cases 4 t

Extension Instruction Specifications3-38<Error actualizing condition>Error actualizing condition is generated by the first extension instruction

Extension Instruction Specifications3-39In addition, please obey the following recommended conditions of 3 points when a program is developed by theas

Extension Instruction Specifications3-40

4. Memory Modes34

Memory Modes4-24.1 Memory Mode Types and SelectionThis microcontroller has a 32-bit linear address space of up to 4 Gbytes.The address space is compri

Memory Modes4-34.2 Memory Mode Pin ProcessingFix the input levels for the memory mode pins (MMOD0,1) as shown in Table 4-2-1 and Fig. 4-2-1 w